Clock synchronization on a network is affected by time delay ascribable to congestion on the network or by fluctuations in the processing time at a device interfacing unit. In case a wireless communication link is established between a clock master side device that generates a master clock and a clock slave side device that synchronizes the clock of the own device based on the master clock as a reference, fluctuations may be of a large magnitude. In such case, the state of transmission may be stable only on rare occasions. If, under such condition, the synchronization information received by the clock slave side device is directly processed with a clock synchronization correction operation, fluctuation components are superposed on the corrected value, such that correct clock synchronization may not be achieved.
In Patent Document 1 (JP Patent Kokai Publication No. JP-P2003-198519A), for example, which seeks to solve the problem that, in case a plurality of reference clocks are provided, and are referenced as they are interchanged, the reference clocks are not necessarily in phase with one another such that a generated clock references a new one of the reference clocks, on interchanging of the reference clocks, the generated clock follows the phase of the new reference clock, discloses a method for clock generation that uses a frequency measurement unit for measuring the frequency of each of the reference clocks and a frequency adjustment unit that matches the frequency of an output clock to the frequency of the reference clock. The generated clock is synchronized with the reference clock based on the frequency of the reference clock, as a reference, thereby eliminating phase transition of the generated clock as well as eliminating data slip. The generated clock is free from phase transition even in case the reference clocks are interchanged a plurality of numbers of times.
Patent Document 2 (JP Patent Kokai Publication No. JP-P2007-274612A) discloses a PLL device in which the signal level of a reference frequency signal supplied externally is monitored, and in which, when the signal level is within a predetermined range, PLL control is exercised using phase difference related data prepared by a phase difference data formulation means. In case the signal level is outside the predetermined range, it is determined that the signal supply has ceased or an unusual situation has occurred. In this case, the phase difference data is switched to the phase difference related data stored in a storage unit, for example, the latest stored data or data generated at the outset, in order to exercise PLL (phase synchronization loop) control.
Patent Document 3 (JP Patent Kokai Publication No. JP-P2004-186877A) discloses a wireless access network system, a wireless communication system, a synchronization server and a node device. The radio access network system includes a clock generator that periodically generates a clock, and a synchronization message generator that generates a synchronization message for notification of the information regarding the clock generated. The radio access network system also includes an IP packet transmission/processing unit that transmits a synchronization message to each node as IP packet. The radio access network system also includes an IP packet reception processor that receives the synchronization message at each node, and a transmission/reception time point calculation unit that acquires the time of reception of the synchronization message. The radio access network system further includes a clock correction processor that calculates a clock correction value based on the time of receipt acquired by the transmission/reception time calculation unit and on the clock related information notified by the synchronization message to correct the clock at each node based on this clock correction value.
Patent Document 4 (JP Patent Kokai Publication No. JP-P2008-177913A) discloses a communication apparatus and a clock reproducing method. In a slave side unit, a transmission/reception time interval comparator sets, in a received packet, the time information for the slave side unit and the sequence information contained in the received packet. Based on the time information and the sequence information of reception, as well as the time information of transmission and the sequence information, contained in the packet, at least one out of the interchange in the packet arrival sequence of received packets and packet dropout is checked. The interval of the time information of transmission and that of the time information of reception are calculated under control conforming to the result of the check. The difference between the interval of the time information of transmission and that of the time information of reception is calculated as being the transmission/reception time information interval. A smoothing unit smoothes a plurality of packets over a time information interval corresponding to a value calculated under control conforming to the result of the check to correct the offset contained in packets before and following the packet checked.    [Patent Document 1]
JP Patent Kokai Publication No. JP P2003-198519A    [Patent Document 2]
JP Patent Kokai Publication No. JP P2007-274612A    [Patent Document 3]
JP Patent Kokai Publication No. JP P2004-186877A    [Patent Document 4]
JP Patent Kokai Publication No. JP P2008-177913A